Digineuron

This project aims to obtain compact and powerful archi­tec­tures to imple­ment Neural Networks on chip. The combined used of time encoding, through an appro­priate nonlinear encoding of inputs, compu­ta­tion in time and event-based process­ing can lead to new Neural Network archi­tec­tures, which are more compact in area and require less energy than conven­tional vector-vector prod­ucts or spike-based compu­ta­tion.

The main objec­tives of this project are large event-based neural networks on chip when the stimuli are sparse in time with the aim of reducing the computing energy and area, time-based coding in hard­ware using memory-based compu­ta­tion, thus avoiding the use of multi­pli­ca­tions that take up most of the space in IC designs and building a demon­strator with a System-on-chip (SoC) imple­menting a camera plus dedi­cated accel­er­a­tors, and an FPGA mounted on a dedi­cated PCB that will also host the optics for the camera. To achieve that, basic algo­rithms will be simu­lated to compare different alter­na­tives and estab­lish a compar­ison at a high level of abstrac­tion.

The imple­men­ta­tion and training of NN will be performed in PyTorch and other similar open plat­forms. Also, analog and mixed signal circuits will be designed and simu­lated at the schematics level in the Cadence / Synopsys plat­forms avail­able at Silicon Austria Labs. The work carried out in this project lays the foun­da­tion for several appli­ca­tions in 6G Systems, Industry 4.0, IOT, remote sensing, Ultra­sound sensing and medical appli­ca­tions and commu­ni­ca­tions with strict energy and compu­ta­tional constraints. The IC cores devel­oped for DNNs can act as a general frame­work for inte­grating intel­li­gence on to the chip and to realize several ad-hoc IoT based appli­ca­tions.