DIGINEURON

This project aims to obtain compact and powerful architectures to implement Neural Networks on chip. The combined used of time encoding, through an appropriate nonlinear encoding of inputs, computation in time and event-based processing can lead to new Neural Network architectures, which are more compact in area and require less energy than conventional vector-vector products or spike-based computation.

The main objectives of this project are large event-based neural networks on chip when the stimuli are sparse in time with the aim of reducing the computing energy and area, time-based coding in hardware using memory-based computation, thus avoiding the use of multiplications that take up most of the space in IC designs and building a demonstrator with a System-on-chip (SoC) implementing a camera plus dedicated accelerators, and an FPGA mounted on a dedicated PCB that will also host the optics for the camera. To achieve that, basic algorithms will be simulated to compare different alternatives and establish a comparison at a high level of abstraction.

The implementation and training of NN will be performed in PyTorch and other similar open platforms. Also, analog and mixed signal circuits will be designed and simulated at the schematics level in the Cadence / Synopsys platforms available at Silicon Austria Labs. The work carried out in this project lays the foundation for several applications in 6G Systems, Industry 4.0, IOT, remote sensing, Ultrasound sensing and medical applications and communications with strict energy and computational constraints. The IC cores developed for DNNs can act as a general framework for integrating intelligence on to the chip and to realize several ad-hoc IoT based applications.