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We develop trustworthy, efficient, and deployable AI systems for edge environments by combining collaborative AI methods with next-generation hardware acceleration. With expertise spanning the entire stack—from software and algorithms to hardware architecture and chip design—the unit pursues an end-to-end co-design approach to edge intelligence.
Our research integrates explainable and verifiable distributed AI, privacy-preserving learning, and hybrid accelerators into the RISC-V hardware/software ecosystem. In this way, we create AI systems that meet requirements for energy efficiency, scalability, security, and suitability for safety-critical and regulated sectors.
The unit combines the expertise of the “Trustworthy and Efficient Collaborative AI” (TEC-AI) team, which focuses on trustworthy and collaborative edge AI, with that of the “Hardware Accelerators and Design” (HAND) team, which specializes in hardware-software co-design and domain-specific accelerators.
The TEC-AI team’s work focuses on developing trustworthy AI for edge and distributed environments and encompasses federated learning, federated distillation, and multi-agent reinforcement learning. The team develops explainable and formally verified AI systems and applies adaptive shielding in conjunction with machine learning to meet the requirements of safety-critical applications. Targeted efforts toward efficient AI deployment ensure that these solutions remain viable even on resource-constrained edge platforms.
The HAND team’s research expertise encompasses domain-specific AI architectures as well as compile-time middleware, profiling, and runtime support, including support for post-quantum-secure cryptography. Its hardware/software co-design approach, based on RISC-V and custom accelerators, paves the way for secure edge learning and end-to-end AI integration.
Collaborative Intelligence for E-Mobility and Energy Systems
Model-Based Verification & Safe Learning for Trustworthy AI
Post-Quantum Cryptography for Secure Embedded Systems
Computational Accelerators on Resource-Constrained Hardware