RFIC Design for PLL/Frequency Synthesizers
Science Park 1, Altenberger Straße 69, 4040 Linz, Austria

Silicon Austria Labs is performing cutting-edge research in its world-class mmWave RF Lab on the physical layer of RF systems for future 5G/6G (UE, front and back-haul), and millimeter-wave imaging/sensing/radar applications. In this domain, the mmWave RF Lab collaborates closely with the Johannes Kepler University Linz and leading industry partners on e.g. RF/millimeter-wave transceiver architectures robust in terms of interference and coexistence, reconfigurable RF systems for transceivers and RF/millimeter-wave front-end modules (architectural reuse and/or resource sharing), and large-scale phased-array antennas and beamforming structures, which are targeting millimeter-wave and sub-Terahertz communications (5G, 6G), radars and imagers. In support of the design activities the mmWave RF Lab is equipped with the best in-class test infrastructure covering the GHz and low THz frequency range.

Your future responsibilities

  • System and circuit solutions for multi-gigabit wireless chips
  • Frequency synthesizer/PLL architecture selection Implementing blocks and documenting design towards formal design reviews
  • Drive layout and top-level simulations to validate top-level  integration
  • Take lab measurements to validate analog designs

Your profile

  • Solid experience in
    • PLL or clock/frequency generation design  
    • Understanding of RF/high-speed (10GHz+) issues  Performing analog custom layout 
    • Phase noise/jitter, BW & power consumption design  trade-offs
  • High proficiency in system specification & ability to translate system into circuit requirements at IC level 
  • Deep understanding of fundamentals, including
    • Detailed transistor level design
    • Control/feedback loop stability analysis  
    • Device physics is a plus
  • Design experience in advanced CMOS nodes (FD-SOI, FinFET, bulk) is a plus 
  • Insights into packaging effects, supply isolations, high frequency ESD structures & circuit layout for optimum   performance 
  • Experience in simulation and design of lumped &  distributed passive structures 
  • Using EDA CAD tools (Cadence, Synopsys, Mentor, Ansys, etc.) Proven experience in measuring IC performance and debug of design to correlate simulations to measurements Master or PhD degree in relevant field with 5+ years of experience

Important facts

  • Beginning of the employment: as soon as possible
  • This position is endowed with a gross annual salary of  € 42,742 based on the collective agreement for research  („Forschungs-Kollektivvertrag“) and depending on your  experience and skills.


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