Circuit Topo­lo­gies & Design Metho­do­lo­gies for High Data-Rate mm-Wave Radio Trans­cei­vers

Sorin Voinigescu
JKU Linz
SCP1, MT327
Altenberger Straße 69
4040 Linz

On Dec. 12th Prof. Sorin Voini­gescu, Depart­ment of Electrical and Computer Engi­nee­ring Univer­sity of Toronto, will give a talk at Science Park in Linz. This event is jointly orga­nized by the IEEE Austria CAS/​SSC Joint Chapter, JKU, LCM and SAL Silicon Austria Labs.

This presen­ta­tion will explore fully digital archi­tec­tures and circuit topo­lo­gies for future wire­less back­haul systems with aggre­gate data rates compa­rable to those of future 64Gbaud fibe­r­optic systems. The main features of FD-SOI CMOS tech­no­logy and how to effi­ci­ently use its unique features for RF and mm-wave SoCs will be reviewed first.

We will discuss the impact of the back­gate bias on the measured I-V, trans­con­duc­tance, fT and fMAX charac­te­ris­tics and compare the MAG of FDSOI MOSFETs with those of planar bulk CMOS, SOI and SiGe BiCMOS tran­sis­tors through measu­re­ments up to 325 GHz. I will provide exam­ples of FDSOI LNA, mixer, swit­ches, and PA circuit topo­lo­gies and layouts that make effi­cient use of the back-gate bias to over­come the limi­ta­tions asso­ciated with the low break­down voltage of sub-28nm CMOS tech­no­lo­gies.

Exam­ples of measured 45nm SOI CMOS digital trans­mit­ters with free space constel­la­tion forma­tion at 100 GHz and 140 GHz will be provided along with a 1-30GHz fully digital I-Q trans­mitter with 20 dBm output power for 5G termi­nals. Finally, Predis­tor­tion and spec­tral shaping tech­ni­ques in the trans­mitter, and receiver ADC-based equa­liza­tion at 64 GBaud will be discussed.